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ds05-50209-4e fujitsu semiconductor data sheet stacked mcp (multi-chip package) flash memory & fcram cmos 64 m ( 16) flash memory & 16 m ( 16) sram interface fcram mb84vd23381ej -85 / 90 n n n n features ? power supply voltage of 2.7 v to 3.1 v for fcram ? power supply voltage of 2.7 v to 3.3 v for flash ? high performance 85 ns maximum access time (flash) 85 ns maximum access time (fcram) ? operating temperature - 30 c to + 85 c ? package 101 - ball fbga (continued) n n n n product line-up *: both v cc f and v cc s must be the same level when either part is being accessed. n n n n pac k ag e mb84vd23381ej-90 guarantees both fcram and flash at 85 ns access cycle. flash memory fcram power supply voltage ( v ) v cc f* = 2.7 v to 3.3 v v cc s* = 2.7 v to 3.1 v max address access time (ns) 85 85 max c e access time (ns) 85 85 max o e access time (ns) 35 50 101-ball plastic fbga (bga-101p-m01)
mb84vd23381ej -85/90 2 (continued) flash memory ? simultaneous read / write operations ( flex bank ) two virtual banks are chosen from the combination of four physical banks. host system can program or erase in one bank, then immediately and simultaneously read from the other bank. zero latency between read and write operations. read-while-erase read-while-program ? minimum 100,000 write / erase cycles ? sector erase architecture sixteen 4 kwords and one hundred twenty-six 32 kword sectors. any combination of sectors can be concurrently erased. the device also supports full chip erase. ? embedded erase tm *algorithms automatically pre-programs and erases the chip or any sector. ? embedded program tm *algorithms automatically writes and verifies data at specified address. ? data polling and toggle bit feature for detection of program or erase cycle completion ? ready-busy output ( ry / by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ? low v cc write prohibition 2.5 v ? hidden rom ( hi-rom ) region 256 byte of hi-rom, accessible through a new hi-rom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp / acc input pin allows protection of outermost 2 8 kbytes on both ends of boot sectors at v il , regardless of sector protection/ unprotection status. allows removal of boot sector protection at v ih . increases program performance at v acc . ? program suspend / resume suspends the program operation to allow a read in another byte. ? erase suspend / resume suspends the erase operation to allow reading in another sector within the same device. ? please refer to mbm29dl640e datasheet for detailed functions. fcram ? power dissipation operating : 20 ma max standby : 70 m a max power down : 10 m a max ? power down control by ce2s ? byte write control : lb s ( dq 7 -dq 0 ) , ub s ( dq 15 -dq 8 ) ? 4 words address access capability *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mb84vd23381ej -85/90 3 n n n n pin assignment fbga (top view) marking side (bga-101p-m01) a12 a11 a10 b12 b11 b10 c12 c11 c10 m12 m11 m10 n12 n11 n10 o12 o11 o10 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. g11 g10 g9 n.c. n.c. a 14 g8 a 10 h11 h10 h9 n.c. a 16 n.c. h8 dq 6 j10 j9 v cc f dq 15 j8 dq 13 j7 j6 dq 4 dq 3 j5 dq 9 j4 oe j3 cef a3 a2 a1 b3 b2 b1 c3 c2 c1 m3 m2 m1 n3 n2 n1 o3 o2 o1 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. d2 n.c. d9 a 11 d8 a 8 d7 we d6 wp/acc d5 lb s d4 a 7 n.c. c7 c6 n.c. n.c. e10 a 15 e9 a 12 e8 a 19 e7 ce2s e6 reset e5 e4 ub s a 6 e3 a 3 f10 a 21 f9 a 13 f8 a 9 f7 a 20 f6 ry/by f5 f4 a 18 a 5 f3 a 2 g5 g4 a 17 a 4 g3 a 1 g2 n.c. h5 h4 dq 1 v ss h3 a 0 h2 n.c. k10 k9 v ss dq 7 k8 dq 12 k7 k6 v cc s v cc f k5 dq 10 k4 dq 0 l9 dq 14 l8 dq 5 l7 l6 n.c. dq 11 m7 m6 n.c. n.c. l5 dq 2 l4 dq 8 k3 ce1s n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c.
mb84vd23381ej -85/90 4 n n n n pin description pin name function input/output a 19 to a 0 address inputs (common) i a 21 , a 20 address input (flash) i dq 15 to dq 0 data inputs/outputs (common) i/o ce f chip enable (flash) i ce1 s chip enable (fcram) i ce2s chip enable (fcram) i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (flash) open drain output o ub s upper byte control (fcram) i lb s lower byte control (fcram) i reset hardware reset pin/sector protection unlock (flash) i wp /acc write protect/acceleration (flash) i n.c. no internal connection ? v ss device ground (common) power v cc f device power supply (flash) power v cc s device power supply (fcram) power
mb84vd23381ej -85/90 5 n n n n block diagram v cc fv ss v cc sv ss ry/by a 21 to a 0 a 19 to a 0 a 21 to a 0 wp/acc reset cef lbs ubs we oe ce1s ce2s 64 mbit flash memory 16 mbit fcram dq 15 to dq 0 dq 15 to dq 0 dq 15 to dq 0
mb84vd23381ej -85/90 6 n n n n device bus operations user bus operations legend : l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. *1: other operations except for this indicated table are prohibited. *2: do not apply ce f = v il , ce1 s = v il and ce2s = v ih all at once. *3: fcram output disable condition should not be kept longer than 1 m s. *4: we can be v il if oe is v il , oe at v ih initiates the write operations. *5: fcram byte control at read operation is not supported. *6: it is also used for the extended sector group protections. *7: protect outermost 2 8 kbytes (4 words) on both ends of the boot block sectors. *8: power down mode can be entered from standby state and all dq pins are in high-z state. operation * 1, * 2 ce fce1 sce2s oe we lb sub s dq 7 to dq 0 dq 15 to dq 8 reset wp /acc* 7 full standby h h h x x x x high-z high-z h x output disable * 3 h l h h h x x high-z high-z hx l h h h h x x high-z high-z read from flash * 4 lh hlhxx d out d out hx write to flash l h h h l x x d in d in hx read from fcram * 5 hl hlhxx d out d out hx write to fcram h l h h l ll d in d in hx hl high-z d in lh d in high-z temporary sector group unprotection * 6 xx xxxxx x x v id x flash hardware reset x h h x x x x high-z high-z l x boot block sector write protection xx xxxxx x x x l fcram power down* 8 xx lxxxx x x x x
mb84vd23381ej -85/90 7 n n n n flexible sector-erase architecture on flash memory ? sixteen 4 k words, and one hundred twenty-six 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. sa0 : 8 kb (4 kw) sa1 : 8 kb (4 kw) sa2 : 8 kb (4 kw) sa3 : 8 kb (4 kw) sa4 : 8 kb (4 kw) sa5 : 8 kb (4 kw) sa6 : 8 kb (4 kw) sa7 : 8 kb (4 kw) sa8 : 64 kb (32 kw) sa9 : 64 kb (32 kw) sa10 : 64 kb (32 kw) sa11 : 64 kb (32 kw) sa12 : 64 kb (32 kw) sa13 : 64 kb (32 kw) sa14 : 64 kb (32 kw) sa15 : 64 kb (32 kw) sa16 : 64 kb (32 kw) sa17 : 64 kb (32 kw) sa18 : 64 kb (32 kw) sa19 : 64 kb (32 kw) sa20 : 64 kb (32 kw) sa21 : 64 kb (32 kw) sa22 : 64 kb (32 kw) sa23 : 64 kb (32 kw) sa24 : 64 kb (32 kw) sa25 : 64 kb (32 kw) sa26 : 64 kb (32 kw) sa27 : 64 kb (32 kw) sa28 : 64 kb (32 kw) sa29 : 64 kb (32 kw) sa30 : 64 kb (32 kw) sa31 : 64 kb (32 kw) sa32 : 64 kb (32 kw) sa33 : 64 kb (32 kw) sa34 : 64 kb (32 kw) sa35 : 64 kb (32 kw) sa36 : 64 kb (32 kw) sa37 : 64 kb (32 kw) sa38 : 64 kb (32 kw) sa39 : 64 kb (32 kw) sa40 : 64 kb (32 kw) sa41 : 64 kb (32 kw) sa42 : 64 kb (32 kw) sa43 : 64 kb (32 kw) sa44 : 64 kb (32 kw) sa45 : 64 kb (32 kw) sa46 : 64 kb (32 kw) sa47 : 64 kb (32 kw) sa48 : 64 kb (32 kw) sa49 : 64 kb (32 kw) sa50 : 64 kb (32 kw) sa51 : 64 kb (32 kw) sa52 : 64 kb (32 kw) sa53 : 64 kb (32 kw) sa54 : 64 kb (32 kw) sa55 : 64 kb (32 kw) sa56 : 64 kb (32 kw) sa57 : 64 kb (32 kw) sa58 : 64 kb (32 kw) sa59 : 64 kb (32 kw) sa60 : 64 kb (32 kw) sa61 : 64 kb (32 kw) sa62 : 64 kb (32 kw) sa63 : 64 kb (32 kw) sa64 : 64 kb (32 kw) sa65 : 64 kb (32 kw) sa66 : 64 kb (32 kw) sa67 : 64 kb (32 kw) sa68 : 64 kb (32 kw) sa69 : 64 kb (32 kw) sa70 : 64 kb (32 kw) bank b bank a 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0a0000h 0a8000h 0b0000h 0b8000h 0c0000h 0c8000h 0d0000h 0d8000h 0e0000h 0e8000h 0f0000h 0f8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1a0000h 1a8000h 1b0000h 1b8000h 1c0000h 1c8000h 1d0000h 1d8000h 1e0000h 1e8000h 1f0000h 1f8000h 1fffffh sa71 : 64 kb (32 kw) sa72 : 64 kb (32 kw) sa73 : 64 kb (32 kw) sa74 : 64 kb (32 kw) sa75 : 64 kb (32 kw) sa76 : 64 kb (32 kw) sa77 : 64 kb (32 kw) sa78 : 64 kb (32 kw) sa79 : 64 kb (32 kw) sa80 : 64 kb (32 kw) sa81 : 64 kb (32 kw) sa82 : 64 kb (32 kw) sa83 : 64 kb (32 kw) sa84 : 64 kb (32 kw) sa85 : 64 kb (32 kw) sa86 : 64 kb (32 kw) sa87 : 64 kb (32 kw) sa88 : 64 kb (32 kw) sa89 : 64 kb (32 kw) sa90 : 64 kb (32 kw) sa91 : 64 kb (32 kw) sa92 : 64 kb (32 kw) sa93 : 64 kb (32 kw) sa94 : 64 kb (32 kw) sa95 : 64 kb (32 kw) sa96 : 64 kb (32 kw) sa97 : 64 kb (32 kw) sa98 : 64 kb (32 kw) sa99 : 64 kb (32 kw) sa100 : 64 kb (32 kw) sa101 : 64 kb (32 kw) sa102 : 64 kb (32 kw) sa103 : 64 kb (32 kw) sa104 : 64 kb (32 kw) sa105 : 64 kb (32 kw) sa106 : 64 kb (32 kw) sa107 : 64 kb (32 kw) sa108 : 64 kb (32 kw) sa109 : 64 kb (32 kw) sa110 : 64 kb (32 kw) sa111 : 64 kb (32 kw) sa112 : 64 kb (32 kw) sa113 : 64 kb (32 kw) sa114 : 64 kb (32 kw) sa115 : 64 kb (32 kw) sa116 : 64 kb (32 kw) sa117 : 64 kb (32 kw) sa118 : 64 kb (32 kw) sa119 : 64 kb (32 kw) sa120 : 64 kb (32 kw) sa121 : 64 kb (32 kw) sa122 : 64 kb (32 kw) sa123 : 64 kb (32 kw) sa124 : 64 kb (32 kw) sa125 : 64 kb (32 kw) sa126 : 64 kb (32 kw) sa127 : 64 kb (32 kw) sa128 : 64 kb (32 kw) sa129 : 64 kb (32 kw) sa130 : 64 kb (32 kw) sa131 : 64 kb (32 kw) sa132 : 64 kb (32 kw) sa133 : 64 kb (32 kw) sa134 : 8 kb (4 kw) sa135 : 8 kb (4 kw) sa136 : 8 kb (4 kw) sa137 : 8 kb (4 kw) sa138 : 8 kb (4 kw) sa139 : 8 kb (4 kw) sa140 : 8 kb (4 kw) sa141 : 8 kb (4 kw) bank d bank c 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2a0000h 2a8000h 2b0000h 2b8000h 2c0000h 2c8000h 2d0000h 2d8000h 2e0000h 2e8000h 2f0000h 2f8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3a0000h 3a8000h 3b0000h 3b8000h 3c0000h 3c8000h 3d0000h 3d8000h 3e0000h 3e8000h 3f0000h 3f8000h 3f9000h 3fa000h 3fb000h 3fc000h 3fd000h 3fe000h 3ff000h 3fffffh sector architecture
mb84vd23381ej -85/90 8 example of virtual banks combination bank a : address 000000h to 07ffffh bank b : address 080000h to 1fffffh bank c : address 200000h to 37ffffh bank d : address 380000h to 3fffffh bank splits bank 1 bank 2 volume combination sector size volume combination sector size 18 mbit bank a 8 8 kbyte/4 kword + 15 64 kbyte/32 kword 56 mbit bank b + bank c + bank d 8 8 kbyte/4 kword + 111 64 kbyte/32 kword 216 mbit bank a + bank d 16 8 kbyte/4 kword + 30 64 kbyte/32 kword 48 mbit bank b + bank c 96 64 kbyte/32 kword 3 24 mbit bank b 48 64 kbyte/32 kword 40 mbit bank a + bank c + bank d 16 8 kbyte/4 kword + 78 64 kbyte/32 kword 432 mbit bank a + bank b 8 8 kbyte/4 kword + 63 64 kbyte/32 kword 32 mbit bank c + bank d 8 8 kbyte/4 kword + 63 64 kbyte/32 kword
mb84vd23381ej -85/90 9 sector address tables (continued) bank sector sector address address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa00000000000 00 0000h to 000fffh sa10000000001 00 1000h to 001fffh sa20000000010 00 2000h to 002fffh sa30000000011 00 3000h to 003fffh sa40000000100 00 4000h to 004fffh sa50000000101 00 5000h to 005fffh sa60000000110 00 6000h to 006fffh sa70000000111 00 7000h to 007fffh sa80000001xxx 008 000h to 00ffffh sa90000010xxx 01 0000h to 017fffh sa100000011xxx 018 000h to 01ffffh sa110000100xxx 02 0000h to 027fffh sa120000101xxx 028 000h to 02ffffh sa130000110xxx 03 0000h to 037fffh sa140000111xxx 038 000h to 03ffffh sa150001000xxx 04 0000h to 047fffh sa160001001xxx 048 000h to 04ffffh sa170001010xxx 05 0000h to 057fffh sa180001011xxx 058 000h to 05ffffh sa190001100xxx 06 0000h to 067fffh sa200001101xxx 068 000h to 06ffffh sa210001110xxx 07 0000h to 077fffh sa220001111xxx 078 000h to 07ffffh bank b sa230010000xxx 08 0000h to 087fffh sa240010001xxx 088 000h to 08ffffh sa250010010xxx 09 0000h to 097fffh sa260010011xxx 098 000h to 09ffffh sa270010100xxx 0a 0000h to 0a7fffh sa280010101xxx 0a8 000h to 0affffh sa290010110xxx 0b 0000h to 0b7fffh sa300010111xxx 0b8 000h to 0bffffh sa310011000xxx 0c 0000h to 0c7fffh sa320011001xxx 0c8 000h to 0cffffh
mb84vd23381ej -85/90 10 (continued) bank sector sector address address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa330011010xxx 0d00 00h to 0d7fffh sa340011011xxx 0d8000h to 0dffffh sa350011100xxx 0e0000h to 0e7fffh sa360011101xxx 0e8000h to 0effffh sa370011110xxx 0f00 00h to 0f7fffh sa380011111xxx 0f8000h to 0fffffh sa390100000xxx 100000h to 107fffh sa400100001xxx 1 08000h to 10ffffh sa410100010xxx 110000h to 117fffh sa420100011xxx 1 18000h to 11ffffh sa430100100xxx 120000h to 127fffh sa440100101xxx 1 28000h to 12ffffh sa450100110xxx 130000h to 137fffh sa460100111xxx 1 38000h to 13ffffh sa470101000xxx 140000h to 147fffh sa480101001xxx 1 48000h to 14ffffh sa490101010xxx 150000h to 157fffh sa500101011xxx 1 58000h to 15ffffh sa510101100xxx 160000h to 167fffh sa520101101xxx 1 68000h to 16ffffh sa530101110xxx 170000h to 177fffh sa540101111xxx 1 78000h to 17ffffh sa550110000xxx 180000h to 187fffh sa560110001xxx 1 88000h to 18ffffh sa570110010xxx 190000h to 197fffh sa580110011xxx 1 98000h to 19ffffh sa590110100xxx 1a0000h to 1a7fffh sa600110101xxx 1a8000h to 1affffh sa610110110xxx 1b0000h to 1b7fffh sa620110111xxx 1b8000h to 1bffffh sa630111000xxx 1c00 00h to 1c7fffh sa640111001xxx 1c8000h to 1cffffh sa650111010xxx 1d00 00h to 1d7fffh sa660111011xxx 1d8000h to 1dffffh
mb84vd23381ej -85/90 11 (continued) bank sector sector address address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa670111100xxx 1e0000h to 1e7fffh sa680111101xxx 1e8000h to 1effffh sa690111110xxx 1f00 00h to 1f7fffh sa700111111xxx 1f8000h to 1fffffh bank c sa711000000xxx 200000h to 207fffh sa721000001xxx 2 08000h to 20ffffh sa731000010xxx 210000h to 217fffh sa741000011xxx 2 18000h to 21ffffh sa751000100xxx 220000h to 227fffh sa761000101xxx 2 28000h to 22ffffh sa771000110xxx 230000h to 237fffh sa781000111xxx 2 38000h to 23ffffh sa791001000xxx 240000h to 247fffh sa801001001xxx 2 48000h to 24ffffh sa811001010xxx 250000h to 257fffh sa821001011xxx 2 58000h to 25ffffh sa831001100xxx 260000h to 267fffh sa841001101xxx 2 68000h to 26ffffh sa851001110xxx 270000h to 277fffh sa861001111xxx 2 78000h to 27ffffh sa871010000xxx 280000h to 287fffh sa881010001xxx 2 88000h to 28ffffh sa891010010xxx 290000h to 297fffh sa901010011xxx 2 98000h to 29ffffh sa911010100xxx 2a0000h to 2a7fffh sa921010101xxx 2a8000h to 2affffh sa931010110xxx 2b0000h to 2b7fffh sa941010111xxx 2b8000h to 2bffffh sa951011000xxx 2c00 00h to 2c7fffh sa961011001xxx 2c8000h to 2cffffh sa971011010xxx 2d00 00h to 2d7fffh sa981011011xxx 2d8000h to 2dffffh sa991011100xxx 2e0000h to 2e7fffh sa1001011101xxx 2e8000h to 2effffh
mb84vd23381ej -85/90 12 (continued) bank sector sector address address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa1011011110xxx 2f00 00h to 2f7fffh sa1021011111xxx 2f8000h to 2fffffh sa1031100000xxx 300000h to 307fffh sa1041100001xxx 3 08000h to 30ffffh sa1051100010xxx 310000h to 317fffh sa1061100011xxx 3 18000h to 31ffffh sa1071100100xxx 320000h to 327fffh sa1081100101xxx 3 28000h to 32ffffh sa1091100110xxx 330000h to 337fffh sa1101100111xxx 3 38000h to 33ffffh sa1111101000xxx 340000h to 347fffh sa1121101001xxx 3 48000h to 34ffffh sa1131101010xxx 350000h to 357fffh sa1141101011xxx 3 58000h to 35ffffh sa1151101100xxx 360000h to 367fffh sa1161101101xxx 3 68000h to 36ffffh sa1171101110xxx 370000h to 377fffh sa1181101111xxx 3 78000h to 37ffffh bank d sa1191110000xxx 380000h to 387fffh sa1201110001xxx 3 88000h to 38ffffh sa1211110010xxx 390000h to 397fffh sa1221110011xxx 3 98000h to 39ffffh sa1231110100xxx 3a0000h to 3a7fffh sa1241110101xxx 3a8000h to 3affffh sa1251110110xxx 3b0000h to 3b7fffh sa1261110111xxx 3b8000h to 3bffffh sa1271111000xxx 3c00 00h to 3c7fffh sa1281111001xxx 3c8000h to 3cffffh sa1291111010xxx 3d00 00h to 3d7fffh sa1301111011xxx 3d8000h to 3dffffh sa1311111100xxx 3e0000h to 3e7fffh sa1321111101xxx 3e8000h to 3effffh sa1331111110xxx 3f00 00h to 3f7fffh sa1341111111000 3f80 00h to 3f8fffh
mb84vd23381ej -85/90 13 (continued) bank sector sector address address range bank address a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa1351111111001 3f 9000h to 3f9fffh sa1361111111010 3fa000h to 3fafffh sa1371111111011 3fb000h to 3fbfffh sa1381111111100 3fc000h to 3fcfffh sa1391111111101 3fd000h to 3fdfffh sa1401111111110 3fe000h to 3fefffh sa1411111111111 3ff000h to 3fffffh
mb84vd23381ej -85/90 14 sector group addresses (continued) sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0000000000 sa0 sga1 0000000001 sa1 sga2 0000000010 sa2 sga3 0000000011 sa3 sga4 0000000100 sa4 sga5 0000000101 sa5 sga6 0000000110 sa6 sga7 0000000111 sa7 sga8 00000 01 x x x sa8 to sa10 10 11 sga9 00001 xxxxxsa11 to sa14 sga10 00010 xxxxxsa15 to sa18 sga11 00011 xxxxxsa19 to sa22 sga12 00100 xxxxxsa23 to sa26 sga13 00101 xxxxxsa27 to sa30 sga14 00110 xxxxxsa31 to sa34 sga15 00111 xxxxxsa35 to sa38 sga16 01000 xxxxxsa39 to sa42 sga17 01001 xxxxxsa43 to sa46 sga18 01010 xxxxxsa47 to sa50 sga19 01011 xxxxxsa51 to sa54 sga20 01100 xxxxxsa55 to sa58 sga21 01101 xxxxxsa59 to sa62 sga22 01110 xxxxxsa63 to sa66 sga23 01111 xxxxxsa67 to sa70 sga24 10000 xxxxxsa71 to sa74 sga25 10001 xxxxxsa75 to sa78 sga26 10010 xxxxxsa79 to sa82 sga27 10011 xxxxxsa83 to sa86 sga28 10100 xxxxxsa87 to sa90 sga29 10101 xxxxxsa91 to sa94 sga30 10110 xxxxxsa95 to sa98 sga31 10111 xxxxxsa99 to sa102
mb84vd23381ej -85/90 15 (continued) sector group a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga32 11000 xxxxxsa 103 to sa106 sga33 11001 xxxxxsa 107 to sa110 sga34 11010 xxxxxsa 111 to sa114 sga35 11011 xxxxxsa 115 to sa118 sga36 11100 xxxxxsa 119 to sa122 sga37 11101 xxxxxsa 123 to sa126 sga38 11110 xxxxxsa 127 to sa130 sga39 11111 00 x x x sa131 to sa133 01 10 sga40 1111111000 sa134 sga41 1111111001 sa135 sga42 1111111010 sa136 sga43 1111111011 sa137 sga44 1111111100 sa138 sga45 1111111101 sa139 sga46 1111111110 sa140 sga47 1111111111 sa141
mb84vd23381ej -85/90 16 mb84vd23381ej sector group protection verify autoselect codes *1 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : at word mode, a read cycle at address (ba) 01h outputs device code. when 227eh (at byte mode, 7eh) is output, this indicates that there will require two additional codes, called extended device codes. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh (at byte mode, (ba) 1ch) , as well as at (ba) 0fh. type a 21 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufactures code ba v il v il v il v il v il 04h device code ba v il v il v il v il v ih 227eh extended device code * 2 ba v il v ih v ih v ih v il 2202h ba v il v ih v ih v ih v ih 2201h sector group protection sector group addresses v il v il v il v ih v il 01h *1
mb84vd23381ej -85/90 17 flash memory command definitions *1: this command is valid during fast mode. *2: this command is valid while reset = v id . *3: the valid addresses are (a 6 to a 0 ) . *4: this command is valid during hi-rom mode. *5: the data 00 is also acceptable. notes : address bits a 21 to a 11 = x = h or l for all address commands except for program address (pa) , sector address (sa) , and bank address (ba) . bus operations are defined in user bus operations in device bus operations. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h ? ? ? ??????? read/reset 3 555h aah 2aah 55h 555h f0h ra rd ???? autoselect 3 555h aah 2aah 55h (ba) 555h 90h ?????? program 4 555h aah 2aah 55h 555h a0h pa pd ???? chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend 1bab0h ? ? ? ??????? sector erase resume 1ba30h ? ? ? ??????? program suspend 1 ba b0h ? ? ? ??????? program resume 1 ba 30h ? ? ? ??????? set to fast mode 3 555h aah 2aah 55h 555h 20h ?????? fast program * 1 2 xxxh a0h pa pd ? ??????? reset from fast mode * 1 2 ba 90h xxxh * 5 f0h ? ??????? extended sector group protection * 2 4 xxxh 60h spa 60h spa 40h spa sd ???? query * 3 155h98h ? ? ? ??????? hi-rom entry 3 555h aah 2aah 55h 555h 88h ?????? hi-rom program * 4 4 555h aah 2aah 55h 555h a0h (hra) pa pd ???? hi-rom exit * 4 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h ????
mb84vd23381ej -85/90 18 sa = address of the sector to be erased. the combination of a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 21 to a 19 ) rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the failling edge of the write pulse. spa = sector group address to be protected. set sector group address and (a 6 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 0) . sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hi-rom area (000000h to 000040h) hrba = bank address of the hi-rom area (a 21 = a 20 = a 19 = v il ) the system should generate the following address patterns : 555h or 2aa to addresses (a 10 to a 0 ) . both read/reset commands are functionally equivalent, resetting the device to the read mode.
mb84vd23381ej -85/90 19 n n n n absolute maximum ratings *1: minimum dc voltage on input or i/o pins is C0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to C1.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f+0.3 v or v cc s+0.3 v. during voltage transitions, input or i/o pins may overshoot to v cc f+1.0 v or v cc s+1.0 v for periods of up to 5 ns. *2: minimum dc input voltage on reset pin is C0.5 v. during voltage transitions, reset pin may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (vin-v cc f or v cc s) does not exceed 9.0 v. maximum dc input voltage on reset pin is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *3: minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot vss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +10.5 v for periods of up to 20 ns, when v cc f is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions note: operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 30 + 85 c voltage with respect to ground all pins * 1 v in - 0.3 v cc f + 0.3 v v out - 0.3 v cc s + 0.3 v v cc f supply * 1 v cc f - 0.2 + 3.6 v v cc s supply * 1 v cc s - 0.2 + 3.3 v reset * 2 v in - 0.5 + 13.0 v wp /acc * 3 v in - 0.5 + 10.5 v parameter symbol value unit min max ambient temperature t a - 30 + 85 c v cc f supply voltages v cc f + 2.7 + 3.3 v v cc s supply voltages v cc s + 2.7 + 3.1 v
mb84vd23381ej -85/90 20 n n n n dc characteristics (continued) parameter symbol conditions value unit min typ max input leakage current i li v in = v ss to v cc , v cc = v cc max - 1.0 ?+ 1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max - 1.0 ?+ 1.0 m a reset inputs leakage current i lit v cc = v cc max, reset = 12.5 v ?? 35 m a flash v cc active current (read) * 1 i cc1 fce f = v il , oe = v ih t cycle = 5 mhz ?? 18 ma t cycle = 1 mhz ?? 7ma flash v cc active current (program/erase) * 2 i cc2 fce f = v il , oe = v ih ?? 40 ma flash v cc active current (read-while-program) * 5 i cc3 fce f = v il , oe = v ih ?? 58 ma flash v cc active current (read-while-erase) * 5 i cc4 fce f = v il , oe = v ih ?? 58 ma flash v cc active current (erase-suspend-program) i cc5 fce f = v il , oe = v ih ?? 40 ma fcram v cc active current i cc1 s v cc s = v cc s max, ce1 s = v il , ce2s = v ih , v in = v ih or v il , i out = 0 ma t rc / t wc = min ? 15 20 ma t rc / t wc = 1 m s ? 2.5 3.0 flash v cc standby current i sb1 f v cc f = v cc max, ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v ? 15 m a flash v cc standby current (reset ) i sb2 f v cc f = v cc max, reset = v ss 0.3 v, wp /acc = v cc f 0.3 v ? 15 m a flash v cc current (automatic sleep mode) * 3 i sb3 f v cc f = v cc max, ce f = v ss 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v, v in = v cc f 0.3 v or v ss 0.3 v ? 15 m a fcram v cc standby current i sb s v cc s = v cc s max, ce1 s = ce2s = v ih , v in = v ih or v il , i out = 0 ma ? 0.5 1 ma fcram v cc standby current i sb1 s v cc s = v cc s max, ce1 s > v cc s - 0.2 v, ce2s 3 v cc s - 0.2 v, v in 0.2 v or v cc s - 0.2 v, i out = 0 ma ?? 70 m a fcram v cc standby current i sb2 s v cc s = v cc s max, ce1 s > v cc s - 0.2 v, ce2s 3 v cc s - 0.2 v, v in cycle time = t rc min, i out = 0 ma ?? 5 * 6 ma fcram v cc power down current i pd s v cc s = v cc s max, v in 3 v cc f - 0.2 v or v in 0.2 v ce2s 0.2 v, i out = 0 ma ?? 10 m a
mb84vd23381ej -85/90 21 (contin u ed) *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc is active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: applicable for only v cc applying. *5: embedded alogorithm (program or erase) is in progress. (@5 mhz) *6: i sb 2 s depends on v i n cycle tim e . re f er to n appendix. parameter symbol conditions value unit min typ max input low level v il ?- 0.3 ? 0.5 v input high level v ih ? flash 2.0 ? v cc + 0.3 v fcram 2.2 voltage for autoselect and sector protection (reset ) * 4 v id ? 11.5 ? 12.5 v voltage for wp /acc sector protection/unprotection and program acceleration v acc ? 8.5 9.0 9.5 v fcram output low level v ol v cc s = v cc s min, i ol = 1.0 ma ?? 0.4 v fcram output high level v oh v cc s = v cc s min, i oh = - 0.5 ma 2.1 ?? v flash output low level v ol v cc f = v cc f min, i ol = 4.0 ma ?? 0.45 v flash output high level v oh v cc f = v cc f min, i oh = - 0.1 ma v cc f - 0.4 ?? v low v cc lock-out voltage v lko ? 2.3 ? 2.5 v
mb84vd23381ej -85/90 22 n n n n ac characteristics ce timing timing diagram for alternating fcram to flash parameter symbol condition value unit jedec standard min ce recover time ? t ccr ? 0ns ce hold time ? t chold ? 3ns t ccr t ccr t chold cef ce1s we t ccr t ccr ce2s t chold
mb84vd23381ej -85/90 23 read only operations characteristics (flash) note : test conditions - output load : 1 ttl gate and 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or v cc f timing measurement reference level input : 0.5 v cc f output : 0.5 v cc f parameter symbol conditions value (note) unit jedec standard min max read cycle time t avav t rc ? 85 ? ns address to output delay t avqv t acc ce f = v il oe = v il ? 85 ns chip enable to output delay t elqv t ce foe = v il ? 85 ns output enable to output delay t glqv t oe ?? 35 ns chip enable to output high-z t ehqz t df ?? 30 ns output enable to output high-z t ghqz t df ?? 30 ns output hold time from addresses, ce f or oe , whichever occurs first t axqx t oh ? 0 ? ns reset pin low to read mode ? t ready ?? 20 m s ce f switching low or high ? t elfl t elfh ?? 5ns
mb84vd23381ej -85/90 24 read cycle (flash) hardware reset/read operation timing diagram (flash) address cef oe we outputs output valid address stable t rc t acc t oe t df t oh t ce high-z high-z t oeh address reset outputs output valid address stable t rc t acc t oh t rp t rh t ce t rh high-z cef
mb84vd23381ej -85/90 25 erase/program operations (flash) (continued) parameter symbol value unit jedec standard min typ max write cycle time t avav t wc 85 ?? ns address setup time (we to addr.) t avwl t as 0 ?? ns address setup time to ce f low during toggle bit polling ? t aso 15 ?? ns address hold time (we to addr.) t wlax t ah 45 ?? ns address hold time from ce f or oe high during toggle bit polling ? t aht 0 ?? ns data setup time t dvwh t ds 35 ?? ns data hold time t whdx t dh 0 ?? ns output enable hold time read ? t oeh 0 ?? ns toggle and data polling 10 ?? ns ce f high during toggle bit polling ? t ceph 20 ?? ns ce f high during toggle bit polling ? t oeph 20 ?? ns read recover time before write (oe to ce f) t ghel t ghel 0 ?? ns read recover time before write (oe to we ) t ghwl t ghwl 0 ?? ns we setup time (ce f to we ) t wlel t ws 0 ?? ns cef setup time (we to ce f) t elwl t cs 0 ?? ns we hold time (ce f to we ) t ehwh t wh 0 ?? ns cef hold time (we to ce f) t wheh t ch 0 ?? ns write pulse width t wlwh t wp 35 ?? ns ce f pulse width t eleh t cp 35 ?? ns write pulse width high t whwl t wph 30 ?? ns cef pulse width high t ehel t cph 30 ?? ns word programming operation t whwh1 t whwh1 ? 16 ?m s sector erase operation * 1 t whwh2 t whwh2 ? 1 ? s v cc f setup time ? t vcs 50 ??m s voltage transition time * 2 ? t vlht 4 ??m s rise time to v id * 2 ? t vidr 500 ?? ns rise time to v acc ? t vaccr 500 ?? ns recover time from ry/by ? t rb 0 ?? ns reset pulse width ? t rp 500 ?? ns delay time from embedded output enable ? t eoe ?? 90 ns reset high level period before read ? t rh 200 ?? ns program/erase valid to ry/by delay ? t busy ?? 90 ns
mb84vd23381ej -85/90 26 (continued) *1: this does not include the preprogramming time. *2: this timing is for sector group protection operation. *3: the time between the writes must be less than t tow otherwise that command will not be accepted and erasure will start. a time-out or t tow from the rising edge of last ce f or we whichever happens first will initiate the execution of the sector erase command (s) . *4: when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. parameter symbol value unit jedec standard min typ max erase time-out time * 3 ? t tow 50 ??m s erase suspend transition time * 4 ? t spd ?? 20 m s
mb84vd23381ej -85/90 27 write cycle (we control) (flash) address we oe cef data 3rd bus cycle 555h a0h pd dq 7 d out d out pa pa data polling t wc t cs t wp t ds t dh t oh t df t oe t ce f t wph t whwh1 t ghwl t ch t as t ah t rc notes : pa is an address of the memory location to be programmed. pd is data to be programmed at the word address. d q 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence.
mb84vd23381ej -85/90 28 write cycle (ce f control) (flash) address we oe cef data 3rd bus cycle 555h a0h pd dq 7 d out pa pa data polling t wc t ws t cp t ds t dh t cph t whwh1 t ghel t wh t as t ah notes : pa is the address of the memory location to be programmed. pd is the data to be programmed at the word address. d q 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence.
mb84vd23381ej -85/90 29 ac waveforms chip/sector erase operations (flash) 555h 2aah 2aah 555h 555h t wc t ghwl t as t ah sa * address we oe cef data v cc f t cs t ch t vcs t wph t wp t ds t dh aah 55h 80h aah 55h 10h 30h for sector erase * : sa is the sector address for sector erase. addresses = 555h for chip erase.
mb84vd23381ej -85/90 30 ac waveforms for data polling during embedded algorithm operations (flash) we oe cef dq 7 dq 6 to dq 0 ry/by data data dq 7 = valid data dq 6 to dq 0 valid data t eoe dq 7 dq 6 to dq 0 = output flag t ch t oe t df t oeh t ce f t whwh1 or 2 high-z high-z * t busy * : dq 7 = valid data (the device has completed the embedded operation.)
mb84vd23381ej -85/90 31 ac waveforms for toggle bit during embedded algorithm operations (flash) we cef address oe dq 6 , dq 2 ry/by data t busy t aht t aht t aso t ceph t as t oeh t oeh t cef t dh t oe t oeph * toggle data toggle data toggle data stop toggling output valid * : dq 6 stops toggling (the device has completed the embedded operation.)
mb84vd23381ej -85/90 32 back-to-back read/write timing diagram (flash) address we oe cef dq ba1 ba1 ba1 read valid output valid output valid intput valid intput valid output status ba2 (555h) ba2 (pa) ba2 (pa) t df t dh t ds t oe t ghwl t as t aht t as t acc t ce f t wp t rc t ceph read t rc command t wc read t rc command t wc read t rc t ah t df (pd) (a0h) t oeh note : this is the example of read for bank 1 and embedded algorithm (program) for bank 2 ba1 : address of bank 1 ba2 : address of bank 2
mb84vd23381ej -85/90 33 ry/by timing diagram during write/erase operations (flash) ry/by timing diagram during write/erase operations (flash) the rising edge of the last we signal entire programming or erase operations t busy ry/by we cef ry/by reset we t ready t rp t rb
mb84vd23381ej -85/90 34 temporary sector group unprotection (flash) acceleration mode timing diagram (flash) cef ry/by reset v cc f v ih we v id program or erase command sequence unprotection period t vcs t vidr t vlht t vlht t vlht cef ry/by wp/acc v cc f v ih we v id acceleration mode period t vcs t vaccr t vlht t vlht t vlht
mb84vd23381ej -85/90 35 extended sector group protection (flash) v cc f reset address a 6 , a 3 , a 2 , a 0 a 1 cef data 60h 60h 40h 01h 60h t vcs t vidr t vlht time - out t wp t oe spax spax spay oe we t wc t wc spax : sector group address to be protected spay : next sector group address to be protected time-out : time-out window = 250 m s (min)
mb84vd23381ej -85/90 36 read operation (fcram) *1: the output load is 30 pf. *2: the output load is 5 pf. *3: t ce is applicable if oe is brought to low before ce1 s goes low and is also applicable if actual value of both or either t aso or t clol is shorter than specified value. *4: applicable only to a 0 and a 1 when both ce1 s and oe are kept at low for the address access. *5: applicable if oe is brought to low before ce1 s goes low. *6: t aso , t clol (min) and t op (min) are reference values when the access time is determined by t oe . if actual value of each parameter is shorter than specified minimum value, t oe becomes longer by the amount of subtracting actual value from specified minimum value. for example, if actual t aso , t aso (actual) , is shorter than specified minimum value, t aso (min) , during oe control access (i.e., ce1 s stays low) , t oe becomes t oe (max) + t aso (min) - t aso (actual) . *7: t aso[abs] and t op[abs] are the absolute minimum values during oe control access. *8: if actual value of either t clol or t op is shorter than specified minimum value, both t olah and t olch become t rc (min) - t clol (actual) or t rc (min) - t op (actual) . *9: maximum value is applicable if ce1 s is kept at low. parameter symbol value unit notes min max read cycle time t rc 90 ? ns chip enable access time t ce ? 85 ns *1, *3 output enable access time t oe ? 45 ns *1 chip enable access time t aa ? 85 ns *1, *4 output data hold time t oh 5 ? ns *1 ce1 s low to output low-z t clz 5 ? ns *2 oe low to output low-z t olz 0 ? ns *2 ce1 s high to output high-z t chz ? 30 ns *2 oe high to output high-z t ohz ? 25 ns *2 address setup time to ce1 s low t asc - 5 ? ns *5 address setup time to oe t aso 45 ? ns *3, *6 t aso[abs] 10 ? ns *7 address invalid time t ax ? 5ns*4 ce1 s low to address hold time t clah 90 ? ns *4 oe low to address hold time t olah 45 ? ns *4, *8 ce1 s high to address hold time t chah - 5 ? ns oe high to address hold time t ohah - 5 ? ns ce1 s low to oe low delay time t clol 45 1000 ns *4, *6, *8, *9 oe low to ce1 s high delay time t olch 45 ? ns *8 ce1 s high pulse width t cp 20 ? ns oe high pulse width t op 45 1000 ns *6, *8, *9 t op[abs] 20 ? ns *7
mb84vd23381ej -85/90 37 write operation (fcram) *1: minimum value must be equal or greater than the sum of actual t cw (or t wp ) and t wrc (or t wr ) . *2: new write address is valid from either ce1 s or we that is brought to high. *3: maximum value is applicable if ce1 s is kept at low and both we and oe are kept at high. *4: t oeh is specified from end of t wc (min) , and is a reference value when access time is determined by t oe . if actual value is shorter than specified minimum value, t oe becomes longer by the amount of subtracting actual value from specified minimum value. *5: t oeh[abs] is the absolute minimum value if write cycle is terminated by we and ce1 s stays low. *6: t ohcl (min) must be satisfied if read operation is not performed prior to write operation. in case oe is disabled after t ohcl (min) , we low must be asserted after t rc (min) from ce1 s low. in other words, read operation is initiated if t ohcl (min) is not satisfied. *7: applicable if ce1 s stays low after read operation. *8: t cw and t wp are applicable if write operation is initiated by ce1 s and we , respectively. *9: t wrc and t wr are applicable if write operation is terminated by ce1 s and we , respectively. the t wr (min) can be ignored if ce1 s is brought to high together or after we is brought to high. in such case, t cp (min) must be satisfied. parameter symbol value unit notes min max write cycle time t wc 90 ? ns *1 address setup time t as 0 ? ns *2 address hold time t ah 45 ? ns *2 ce1 s write setup time t cs 0 1000 ns ce1 s write hold time t ch 0 1000 ns we setup time t ws 0 ? ns we hold time t wh 0 ? ns lb s and ub s setup time t bs 0 ? ns lb s and ub s hold time t bh - 5 ? ns oe setup time t oes 0 1000 ns *3 oe hold time t oeh 45 1000 ns *3, *4 t oeh[abs] 20 ? ns *5 oe high to ce1 s low setup time t ohcl - 3 ? ns *6 oe high to address hold time t ohah - 5 ? ns *7 ce1 s write pulse width t cw 60 ? ns *1, *8 we write pulse width t wp 60 ? ns *1, *8 ce1 s write recovery time t wrc 15 ? ns *1, *9 we write recovery time t wr 15 1000 ns *1, *3, *9 data setup time t ds 20 ? ns data hold time t dh 0 ? ns ce1 s high pulse width t cp 20 ? ns *9
mb84vd23381ej -85/90 38 power down parameter (fcram) other timing parameter (fcram) *1: when the parameter t chwx is not satisfied, unintended data may be written into any of the address. *2: must satisfy t chh (min) after t c2lh (min) . *3: requires power down mode entry and exit after t c2hl . *4: the input transition time (t t ) at ac testing is 5 ns as shown below. if actual t t is longer than 5 ns, it may violate ac specification of some timing parameters. ac test conditions (fcram) parameter symbol value unit note min max ce2s low setup time for power down entry t csp 10 ? ns ce2s low hold time after power down entry t c2lp 100 ? ns ce1 s high hold time following ce2s high after power down exit t chh 350 ?m s ce1 s high setup time following ce2s high after power down exit t chs 10 ? ns parameter symbol value unit note min max ce1 s high to oe invalid time for standby entry t chox 20 ? ns ce1 s high to we invalid time for standby entry t chwx 20 ? ns *1 ce2s low hold time after power-up t c2lh 50 ?m s*2 ce2s high hold time after power-up t c2hl 50 ?m s*3 ce1 s high hold time following ce2s high after power-up t chh 350 ?m s*2 input transition time t t 125ns*4 parameter symbol condition value unit note input high level v ih v cc s = 2.7 v to 3.1 v 2.3 v input low level v il v cc s = 2.7 v to 3.1 v 0.4 v input timing measurement level v ref v cc s = 2.7 v to 3.1 v 1.3 v input transition time t t between v il and v ih 5ns
mb84vd23381ej -85/90 39 read timing #1 (oe control access) (fcram) read timing #2 (ce1 s control access) (fcram) ce1s address oe dq (output) t rc t ce t ce t op t oe t olch t ohz t clol t aso t olz t oh t ohz t olz t oh t rc t ohah t aso t ohah address valid address valid valid data output valid data output note : ce2s and we must be high during the entire read cycle. ce1s address oe dq (output) t rc t ce t asc t oe t olch t cp t chz t ce t chz t clz t oh t clz t oh t rc t chah t asc t chah address valid address valid valid data output valid data output note : ce2s and we must be high during the entire read cycle.
mb84vd23381ej -85/90 40 read timing #3 (address access after oe control access) (fcram) ce1s address (a 19 - a 2 ) address (a 1 , a 0 ) oe dq (output) t rc t rc t aso t olah t oe t ohz t olz t oh t oh t ohah t aa t ax address valid address valid valid data output valid data output address valid (no change) address valid note : ce2s and we must be high during the entire read cycle. read timing #3 (address access after oe control access) (fcram) read timing #4 (address access after ce1 s control access) (fcram) ce1s address (a 19 - a 2 ) address (a 1 , a 0 ) oe dq (output) t rc t rc t aso t olah t oe t ohz t olz t oh t oh t ohah t aa t ax address valid address valid valid data output valid data output address valid (no change) address valid note : ce2s and we must be high during the entire read cycle. ce1s address (a 19 - a 2 ) address (a 1 , a 0 ) oe dq (output) t rc t rc t asc t clah t ce t chz t clz t oh t oh t chah t aa t ax address valid address valid valid data output valid data output address valid (no change) address valid note : ce2s and we must be high during the entire read cycle.
mb84vd23381ej -85/90 41 write timing #1 (ce1 s control) (fcram) ce1s address we dq (input) ubs, lbs oe t wc t ws t as t ah t as t cw t wrc t wh t ws t bh t bs t bs t ohcl t ds t dh address valid valid data input note : ce2 s must be high during the entire write cycle.
mb84vd23381ej -85/90 42 write timing #2-1 (we control, single write operetion) (fcram) ce1s address we dq (input) ubs, lbs oe t wc t cs t ohcl t as t ohah t ah t as t cp t ch t wp t wr t bh t bs t oes t ds t ohz t dh address valid valid data input note : ce2 s must be high during the entire write cycle.
mb84vd23381ej -85/90 43 write timing #2 (we control, continuous write operetion) (fcram) ce1s address we dq (input) ubs, lbs oe t wc t cs t ohcl t as t ohah t ah t as t wp t wr t bh t bs t bs t oes t ds t ohz t dh address valid valid data input note : ce2s must be high during the entire write cycle.
mb84vd23381ej -85/90 44 read/write timing #1-1 (ce1 s control) (fcram) ce1s address we dq ubs, lbs oe t wc t ws t wh t cp t as t chah t ah t asc t cw t wrc t wh t ws t bh t bs t ohcl t ds t chz t oh t dh t clz t olz t clol read data output write data input write address read address note : write address is vaild from either ce1 s or we of the last falling edge.
mb84vd23381ej -85/90 45 read/write timing #1-2 (ce1 s control) (fcram) ce1s address we dq ubs, lbs oe t rc t ws t wh t wrc (min) t asc t wrc t chah t as t cp t wh t ws t bs t bh t ce t oeh t dh t clz t oh t chz t ohcl read address write address write data input read data output note : t oeh is specified from the time satisfied both t wrc and t wr (min) .
mb84vd23381ej -85/90 46 read (oe control) /write (we control) timing #2-1 (fcram) ce1s address read data output write data input we dq ubs, lbs oe t wc t wp t as t ah t ohah t aso t wr t bh t bs t oes t oh t ohz t ds t dh t olz t oeh low write address read address note : ce1 s can be tied to low for we and oe controlled operation. when ce1 s is tied to low, output is exclusively controlled by oe .
mb84vd23381ej -85/90 47 read (oe control) / write (we control) timing #2-2 ce1s address read address valid read data output write data input write address we dq ubs, lbs oe t rc t aso t as t ohah t bs t bh t wr t oeh t oe t olz t dh t ohz t oh t oes low note : ce1 s can be tied to low for we and oe controlled operation. when ce1 s is tied to low, output is exclusively controlled by oe .
mb84vd23381ej -85/90 48 power down timing (fcram) standby entry timing after read or write (fcram) t chs t chh t c2lp t csp power down entry power down mode power down exit high-z ce1s ce2s dq t chox t chwx active (read) standby active (write) standby ce1s oe we note : both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period from either last address transition of a0 and a1, or ce1 s low to high transition.
mb84vd23381ej -85/90 49 power-up timing 1 (fcram) power-up timing 2 (fcram) t chh t c2lh t chs * v cc s min 0 v ce1s ce2s v cc s * : it is recommended to keep ce2 s at low during v cc s power-up. the t c2lh is predetermined after v cc s reaches at minimum level. t chh t c2hl t csp v cc s min 0 v ce1s ce2s v cc s t chs t c2lp t c2hl note : the t c2lh specifies from ce2s low to high transition after v ccs reaches specified minimum level. ce1 s must be brought to high prior to or together with ce2s low to high transition.
mb84vd23381ej -85/90 50 n n n n erase and programming performance (flash) n n n n data retention characteristics (fcram) *: 2.0 v v ih v cc s + 0.3 v parameter value unit remarks min typ max sector erase time ? 110s excludes programming time prior to erasure word programming time ? 16 360 m s excludes system-level overhead chip programming time ?? 200 s excludes system-level overhead erase/program cycle 100,000 ?? cycle parameter symbol conditions value unit min typ max v ccs data retention supply voltage v dr ce1 s = ce2s 3 v cc s - 0.2 v or, ce1 s = ce2s = v ih , 2.3 ? 3.1 v v ccs data retention supply current i dr 2.3 v v cc s 2.7 v, v in = v ih (*) or v il ce1 s = ce2s = v ih (*) , i out = 0 ma ? 0.5 1 ma i dr1 2.3 v v cc s 2.7 v, v in 0.2 v or v in 3 v cc s - 0.2 v, ce1 s = ce2s 3 v cc s - 0.2 v, i out = 0 ma ?? 70 m a data retention setup time t drs 2.7 v v cc s 3.1 v at data retention entry 0 ?? ns data retention recovery time t drr 2.7 v v cc s 3.1 v after data retention 90 ?? ns v ccs voltage transition time d v/ d t0.5 ?? v/ m s
mb84vd23381ej -85/90 51 data retention timing n n n n pin capacitance note : test conditions t a = 25 c, f = 1.0 mhz n n n n handling of package please handle this package carefully since the sides of package create acute angles. n n n n caution the high voltage (v id ) cannot apply to address pins and control pins except reset . exception is when autoselect and sector group protect function are used, then the high voltage (v id ) can be applied to reset . without the high voltage (v id ) , sector group protection can be achieved by using extended sector group protection command. parameter symbol condition value unit typ max input capacitance c in v in = 0 v 11 14 pf output capacitance c out v out = 0 v 12 16 pf control pin capacitance c in2 v in = 0 v 14 16 pf wp /acc pin capacitance c in3 v in = 0 v 21.5 26 pf 3.1 v v cc s t drs v cc s 3 0.2 v or v ih ( * ) min t drr d v/ d t d v/ d t ce2s ce1s 2.7 v 2.3 v 0.4 v v ss data retention mode data bus must be in high-z at data retention entry. * : 2.0 v v ih v ccs + 0.3 v
mb84vd23381ej -85/90 52 n n n n ordering information mb84vd23381 ej -85 -pbs device number/description 64 mega-bit (4 m 16-bit) dual operation flash memory 3.0 v-only read, program, and erase 16 mega-bit (1 m 16-bit) fcram pa c k a g e t y p e pbs = 101-ball fbga speed option see product selector guide device revision
mb84vd23381ej -85/90 53 n n n n appendix i sb2 s vs. v in cycle time 2.5 2.0 1.5 1.0 0.5 0.0 v in cycle time (ns) 0 200 400 600 800 1000 : rt = 25 c : lt = - 30 c : ht = 85 c i sb2 s (ma) i sb2 s vs. v in cycle time (v cc s = 3.0 v)
mb84vd23381ej -85/90 54 n n n n package dimension 101-ball plastic fbga (bga-101p-m01) dimensions in mm (inches). c 2000 fujitsu limited b101001s-1c-1 12.00?.10(.472?004) 11.00?.10 (.433?004) index-mark area 0.10(.004) 0.39?.10 (.015?004) (stand off) .049 ?004 +.006 ?.10 +0.15 1.25 (mounting height) 0.80 (.031) 5.60(.220)ref 7.20(.283) 10.40(.409) 0.80 (.031) 5.60(.220) ref 8.80(.346) a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 101-.018 ?002 +.004 ?.05 +0.10 101-0.45 m 0.08(.003)
mb84vd23381ej -85/90 fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0111 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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